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Microarch Club
Trailer
Bonus
Episode 7
Season 1
111: Kay Li
Kay Li joins to talk about custom hardware used in high-frequency trading, development workflows for FPGA and ASIC design, and why verification has become a bottleneck in the design process. We also discuss SiLogy, the startup Kay founded with Paul Kim to improve the design workflow, including their experience applying to and going through YCombinator, their initial target market, and how the platform could evolve over time.
Kay on LinkedIn: https://www.linkedin.com/in/kay-li-84924128b/
Kay on Twitter: https://twitter.com/silikayli
Detailed Show Notes: https://microarch.club/episodes/111
Kay on LinkedIn: https://www.linkedin.com/in/kay-li-84924128b/
Kay on Twitter: https://twitter.com/silikayli
Detailed Show Notes: https://microarch.club/episodes/111
Chapters
- Welcome Kay
- Kay's Introduction to Computing
- Learning Programming with FORTRAN
- Focus on Mathematics
- First Computer
- Intel Pentium III
- Exposure to Computer Science in Northwest Florida
- Math Competitions
- Math Classes at University of West Florida
- Attending University of Chicago
- Realizing Career Wouldn't be as Mathematician
- Family Background in Academia
- László Babai
- Functional Programming
- Elm Language
- Matt Godbolt on Microarch Club
- Getting Into Financial Trading
- Chicago Mercantile Exchange (CME)
- University of Chicago Booth School
- Eric Budish
- The High-Frequency Trading Arms Race
- Flash Boys
- The Value of High-Frequency Trading
- Joining a Trading Firm
- Life as a Quant
- FPGAs in High-Frequency Trading
- The Prevalence of Custom Hardware in High-Frequency Trading
- Previous Exposure to FPGAs
- Benefits of Working at a Small Firm
- First FPGA Programs
- CME Market Data Platform (MDP) FIX Message Format
- Trigger-Based Trading
- Frequency of Reprogramming FPGAs
- HDLs Used in High-Frequency Trading
- Verilog
- Design Verification
- How Verification Works
- Parallelism of Hardware
- Pre-Synthesis Verification
- RTL Testbenches
- Constrained Randomization
- Optimization in FGPA Design
- When FPGAs Aren't Enough
- Prevalence of ASICs in Trading
- Joining Hudson River Trading (HRT)
- Open Source at HRT
- FPGA Design Tooling
- Verilator
- cocotb
- Todd Strader
- How We Verify Custom Hardware at HRT
- Limitations of Open Source Tooling
- Cycle-Based vs. Event-Based Simulators
- Encrypted IP
- 2-State vs. 4-State Data Types
- Post-Synthesis Verification
- Parallelism in FPGA Verification
- Use of IP Blocks in Logic Design
- Debuggability of Proprietary IP Blocks
- Process for Purchasing IP Blocks
- Decision to Leave Hudson River Trading
- Waiting Out a Noncompete
- Prevalence of Noncompetes in Trading
- Learning Rust
- Decision to Start a Company
- Making It Easier to Get Started with FPGAs
- Pain Points in FPGA Development
- Rising Complexity in Chip Design
- Project Euler
- Decision to Join YCombinator
- Place & Route
- Finding a Co-founder
- Paul Kim
- Cloudflare Auth Service
- CEO vs. CTO Role
- YCombinator Application Process
- Brad Flora
- Launching SiLogy
- Framer
- James, SiLogy Founding Engineer
- Naming the Company
- Why Focus on Verification?
- Asianometry Video on the Verification Gap
- Outsourcing of Verification
- Impact of Rising Software Engineering Salaries on Chip Design
- NVIDIA Design Verification Workflow
- Bottlenecks in Verification
- Collaboration in Design Verification
- Currently Supported Tooling on SiLogy
- GitHub Applications
- Comparing SiLogy to General Purpose CI Services
- Early Target Market for SiLogy
- Working with Other Startups
- Tiny Tapeout
- Open Source Process Development Kits (PDK)
- FOSSI LatchUp
- Expanding into Other Parts of Chip Design Workflow
- Possibility of Developing New Tooling
- An IP Block Marketplace
- How to Try SiLogy Today
- The Impact of AI Workloads on Microarchitecture
- CUDA and the Importance of a Software Ecosystem