{"type":"rich","version":"1.0","provider_name":"Transistor","provider_url":"https://transistor.fm","author_name":"Oxide and Friends","title":"Rack-scale Networking","html":"<iframe width=\"100%\" height=\"180\" frameborder=\"no\" scrolling=\"no\" seamless src=\"https://share.transistor.fm/e/e0fc97e0\"></iframe>","width":"100%","height":180,"duration":5667,"description":"Bryan and Adam are joined by a number of members of the Oxide networking team to talk about the networking software that drives the Oxide rack. It turns out that rack-scale networking is hard... and has enormous benefits!\nWe've been hosting a live show weekly on Mondays at 5p for about an hour, and recording them all; here is the recording from February 27th, 2023.\nIn addition to Bryan Cantrill and Adam Leventhal, speakers included Ryan Goodfellow, Levon Tarver, Ben Naecker, and Arjen Roodselaar.\n\nLinks\nIntel Tofino Series\nP4 (programming language) - Wikipedia\np4lang/p4c: P4_16 reference compiler\noxidecomputer/p4: A P4 compiler\nThe quote crate: Rust quasi-quoting\nRIFT WG - Routing In Fat Trees | IETF Community Wiki\nHere's (much of) the live chat from the show:\nahl https://github.com/oxidecomputer/oxide-and-friends/blob/master/2021_11_29.md\nahl That's the Sidecar switch episode\nbcantrill https://p4.org/\nadmchl What does \"at line rate\" mean?\nRiking Line rate = As fast as the packets could possibly come. 1Gbit, 10Gbit, 100Gbit, etc\nadmchl Do you need ASICs to hit that speed? I assume x86_64 is not going to be fast enough for these specialised operations?\nlevon Yes, the Tofino 2 is the ASIC\nbcantrill You need ASICs\nbnaecker Yes, you really can't do these kinds of operations on a general purpose CPU.\nrng_drizzt Yeah, you need specialized silicon here.\nJustinAzoff Right, also often across all ports at the same time in both direction. a 48 port 10gbps switch will have a line rate of 960gbps (10 ** 48 ** 2)\nduckman So the advantage is being able to offload compute to the switch?\nbnaecker Yes, and specifically that you can separate the data plane (operations on the packets) from the control plane (decisions about what operations to allow or make).\ntahnok What's TCAM?\nlevon Ternary Content Addressable Memory\nbnaecker https://en.wikipedia.org/wiki/Content-addressable_memory#Ternary_CAMs\nryaeng Sure beats logging into a number of Cisco switches and making changes at the...","thumbnail_url":"https://img.transistorcdn.com/cVYTzMGAZ_7gNn2i7iJYSuWlQOM4wHdJAzEuWrnLo9A/rs:fill:0:0:1/w:400/h:400/q:60/mb:500000/aHR0cHM6Ly9pbWct/dXBsb2FkLXByb2R1/Y3Rpb24udHJhbnNp/c3Rvci5mbS80OGI3/NjA5NWY4Yjc4NzE0/ZGI5ZmMzZmY4MjFi/YThiYy5wbmc.webp","thumbnail_width":300,"thumbnail_height":300}